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SyncMOS
Functional Block Diagram
F29C51001T/F29C51001B
X-Decoder
1,048,576 Bit Memory Cell Array
A0-A16
Address buffer & latches
Y-Decoder
CE OE WE
Control Logic
I/O Buffer & Data Latches
I/O0-I/O7
51001-05
Capacitance (1,2)
Symbol
CIN COUT CIN2
Parameter
Input Capacitance Output Capacitance Control Pin Capacitance
Test mSetup
VIN = 0 VOUT = 0 VIN = 0
Typ.
6 8 8
Max.
8 12 10
Units
pF pF pF
NOTE: 1. Capacitance is sampled and not 100% tested. 2. TA = 25C, VCC = 5V 10%, f = 1 MHz.
Latch Up Characteristics(1)
Parameter
Input Voltage with Respect to GND on A9, OE Input Voltage with Respect to GND on I/O, address or control pins VCC Current NOTE: 1. Includes all pins except VCC. Test conditions: VCC = 5V, one pin at a time.
Min.
-1 -1 -100
Max.
+13 VCC + 1 +100
Unit
V V mA
AC Test Load
+5.0 V IN3064 or Equivalent Device Under Test IN3064 or Equivalent CL = 100 pF 6.2 k IN3064 or Equivalent IN3064 or Equivalent
51001-06
2.7 k
F29C51001T/F29C51001B V1.0 May 1999
3
SyncMOS
Absolute Maximum Ratings(1)
Symbol
VIN VIN VCC TSTG TOPR IOUT
F29C51001T/F29C51001B
Parameter
Input Voltage (input or I/O pins) Input Voltage (A9 pin, OE) Power Supply Voltage Storage Temerpature (Plastic) Operating Temperature Short Circuit Current(2)
Commercial
-2 to +7 -2 to +13 -0.5 to +5.5 -65 to +125 0 to +70 200 (Max.)
Extended
-2 to +7 -2 to +13 -0.5 to +5.5 -65 to +150 -40 to + 125 200 (Max.)
Unit
V V V C C mA
NOTE: 1. Stress greater than those listed unders "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. No more than one output maybe shorted at a time and not exceeding one second long.
DC Electrical Characteristics
(over the commercial operating range)
Parameter Name
VIL VIH IIL IOL VOL VOH ICC1
Parameter
Input LOW Voltage Input HIGH Voltage Input Leakage Current Output Leakage Current Output LOW Voltage Output HIGH Voltage Read Current
Test Conditions
VCC = VCC Min. VCC = VCC Max. VIN = GND to VCC, VCC = VCC Max. VOUT = GND to VCC, VCC = VCC Max. VCC = VCC Min., IOL = 2.1mA VCC = VCC Min, IOH = -400A CE = OE = VIL, WE = VIH, all I/Os open, Address input = VIL/VIH, at f = 1/tRC Min., VCC = VCC Max. CE = WE = VIL, OE = VIH, VCC = VCC Max. CE = OE = WE = VIH, VCC = VCC Max. CE = OE = WE = VCC - 0.3V, VCC = VCC Max. CE = OE = VIL, WE = VIH CE = OE = VIL, WE = VIH, A9 = VH Max.
Min.
-- 2 -- -- -- 2.4 --
Max.
0.8 -- 1 1 0.4 -- 40
Unit
V V A A V V mA
ICC2 ISB ISB1 VH IH
Program Current TTL Standby Current CMOS Standby Current Device ID Voltage for A9 Device ID Current for A9
-- -- -- 11.5 --
50 2 100 12.5 50
mA mA A V A
F29C51001T/F29C51001B V1.0 May 1999
4
SyncMOS
AC Electrical Characteristics
(over all temperature ranges) Read Cycle
Parameter Name
tRC tAA tACS tOE tCLZ tOLZ tDF tOH
F29C51001T/F29C51001B
-45 Parameter
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time CE Low to Output Active OE Low to Output Active Output Enable or Chip Disable to Output in High Z Output Hold from Address Change
-70 Max.
-- 45 45 25 -- -- 15
-90 Max.
-- 70 70 35 -- -- 20
Min.
45 -- -- -- 0 0 0
Min.
70 -- -- -- 0 0 0
Min.
90 -- -- -- 0 0 0
Max.
-- 90 90 45 -- -- 30
Unit
ns ns ns ns ns ns ns
0
--
0
--
0
--
ns
Program (Erase/Program) Cycle
Parameter Name
tWC tAS tAH tCS tCH tOES tOEH tWP tWPH tDS tDH tWHWH1 tWHWH2 tWHWH3
-45 Parameter
Program Cycle Time Address Setup Time Address Hold Time CE Setup Time CE Hold Time OE Setup Time OE High Hold Time WE Pulse Width WE Pulse Width High Data Setup Time Data Hold Time Programming Cycle Sector Erase Cycle Chip Erase Cycle
-70
-90
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
45 0 35 0 0 0 0 25 20 20 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500 -- -- -- -- -- -- -- -- -- -- -- 20 10 -- 70 0 45 0 0 0 0 35 35 25 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500 -- -- -- -- -- -- -- -- -- -- -- 20 10 -- 90 0 45 0 0 0 0 45 38 30 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 500 -- -- -- -- -- -- -- -- -- -- -- 20 10 -- ns ns ns ns ns ns ns ns ns ns ns s ms ms
F29C51001T/F29C51001B V1.0 May 1999
5
SyncMOS
Waveforms of Read Cycle
tRC ADDRESS tAA CE tCE tOE OE tOLZ WE tCLZ I/O HIGH-Z tOH VALID DATA OUT tAA
F29C51001T/F29C51001B
tDF
VALID DATA OUT
HIGH-Z
51001-07
Waveforms of WE Controlled-Program Cycle
3rd bus cycle tWC tAS ADDRESS 5555H tCH CE PA tAH PA(2) tRC
OE tOES WE tCS tWPH tDS tDH I/O A0H PD(3) I/O7(1) DOUT tOH
51001-08
tWP
tWHWH1
tDF tOE
NOTES: 1. I/O7: The output is the complement of the data written to the device. 2. PA: The address of the memory location to be programmed. 3. PD: The data at the byte address to be programmed.
F29C51001T/F29C51001B V1.0 May 1999
6
SyncMOS
Waveforms of CE Controlled-Program Cycle
tWC ADDRESS 5555H PA tAS tAH WE PA(1)
F29C51001T/F29C51001B
tRC
OE tWP CE tOES tWPH tDS tDH I/O A0H PD(2) I/O7 DOUT tOH
51001-09
tWHWH1
tDF tOE
Waveforms of Erase Cycle(1)
tWC ADDRESS 5555H tAS 2AAAH 5555H tAH CE 5555H 2AAAH SA
OE tWP WE tCS tDS tDH I/O AAH 55H 80H AAH 55H tWPH 10H for Chip Erase 30H
51001-10
NOTES: 1. PA: The address of the memory location to be programmed. 2. PD: The data at the byte address to be programmed. 3. SA: The sector address for Sector Erase. Address = don't care for Chip Erase.
F29C51001T/F29C51001B V1.0 May 1999
7
SyncMOS
Waveforms of DATA Polling Cycle
tCH CE tOE OE tOEH WE tCE tWHWH1 I/O7 I/O7 I/O7
F29C51001T/F29C51001B
tDF
tOH HIGH-Z
VALID DATA OUT
I/O0-I/O6
I/O0-I/O6
INVALID
VALID DATA OUT
HIGH-Z
51001-11
Waveforms of Toggle Bit Cycle
CE tOEH WE
OE
I/O6
51001-12
F29C51001T/F29C51001B V1.0 May 1999
8
SyncMOS
Functional Description
The F29C51001T/F29C51001B consists of 256 equally-sized sectors of 512 bytes each. The 8 KB lockable Boot Block is intended for storage of the system BIOS boot code. The boot code is the first piece of code executed each time the system is powered on or rebooted. The F29C51001 is available in two versions: the F29C51001T with the Boot Block address starting from 1E000H to 1FFFFH, and the F29C51001B with the Boot Block address starting from 00000H to 1FFFFH.
F29C51001T 8KB Boot Block 512 512 * * *
F29C51001T/F29C51001B
F29C51001B 1FFFFH 1E000H 512 512 * * * 512 512 01FFFH 512 00000H 00000H 8KB Boot Block
51001-13
512
Read Cycle
A read cycle is performed by holding both CE and OE signals LOW. Data Out becomes valid only when these conditions are met. During a read cycle WE must be HIGH prior to CE and OE going LOW. WE must remain HIGH during the read operation for the read to complete (see Table 1).
8KB Boot Block = 16 Sectors
Output Disable
Returning OE or CE HIGH, whichever occurs first will terminate the read operation and place the l/O pins in the HIGH-Z state.
During the byte program cycle, addresses are latched on the falling edge of either CE or WE, whichever is last. Data is latched on the rising edge of CE or WE, whichever is first. The byte program cycle can be CE controlled or WE controlled.
Sector Erase Cycle
The F29C51001T/F29C51001B features a sector erase operation which allows each sector to be erased and reprogrammed without affecting data stored in other sectors. Sector erase operation is initiated by using a specific six-bus-cycle sequence: Two unlock program cycles, a setup command, two additional unlock program cycles, and the sector erase command (see Table 2). A sector must be first erased before it can be reprogrammed. While in the internal erase mode, the device ignores any program attempt into the device. The internal erase completion can be determined via DATA polling or toggle bit. The F29C51001T/F29C51001B is shipped with pre-erased sectors (all bits = 1).
Standby
The device will enter standby mode when the CE signal is HIGH. The l/O pins are placed in the HIGH-Z, independent of the OE signal.
Byte Program Cycle
The F29C51001T/F29C51001B is programmed on a byte-by-byte basis. The byte program operation is initiated by using a specific four-buscycle sequence: two unlock program cycles, a program setup command and program data program cycles (see Table 2).
Table 1. Operation Modes Decoding
Decoding Mode
Read Byte Write Standby Autoselect Device ID Autoselect Manufacture ID Enabling Boot Block Protection Lock
CE
VIL VIL VIH VIL VIL VIL
OE
VIL VIH X VIL VIL VH
WE
VIH VIL X VIH VIH VIL
A0
A0 A0 X VIH VIL X
A1
A1 A1 X VIL VIL X
A9
A9 A9 X VH VH VH
I/O
READ PD HIGH-Z CODE CODE X
F29C51001T/F29C51001B V1.0 May 1999
9
SyncMOS
Decoding Mode
Disabling Boot Block Protection Lock Output Disable
F29C51001T/F29C51001B
CE
VH VIL
OE
VH VIH
WE
VIL VIH
A0
X X
A1
X X
A9
VH X
I/O
X HIGH-Z
NOTES: 1. X = Don't Care, VIH = HIGH, VIL = LOW. VH = 12.5V Max. 2. PD: The data at the byte address to be programmed.
Table 2. Command Codes
First Bus Program Cycle Command Sequence Read Read Autoselect Address XXXXH 5555H 5555H Data F0H AAH AAH 2AAAH 2AAAH 55H 55H 5555H 5555H F0H 90H RA 00H 01H RD 40H 01H(1) A1H(2) PD(4) Second Bus Program Cycle Address Data Third Bus Program Cycle Address Data Fourth Bus Program Cycle Address Data Fifth Bus Program Cycle Address Data Six Bus Program Cycle Address Data
Byte Program Chip Erase
5555H
AAH
2AAAH
55H
5555H
A0H
PA
5555H
AAH AAH
2AAAH 2AAAH
55H 55H
5555H 5555H
80H 80H
5555H 5555H
AAH AAH
2AAAH 2AAAH
55H 55H
5555H PA(3)
10H 30H
Sector Erase 5555H
NOTES: 1. Top Boot Sector 2. Bottom Boot Sector 3. PA: The address of the memory location to be programmed. 4. PD: The data at the byte address to be programmed.
Chip Erase Cycle
The F29C51001T/F29C51001B features a chiperase operation. The chip erase operation is initiated by using a specific six-bus-cycle sequence: two unlock program cycles, a setup command, two additional unlock program cycles, and the chip erase command (see Table 2). The chip erase operation is performed sequentially, one sector at a time. When the automated on chip erase algorithm is requested with the chip erase command sequence, the device automatically programs and verifies the entire memory array for an all zero pattern prior to erasure The automatic erase begins on the rising edge of the last WE or CE pulse in the command sequence and terminates when the data on DQ7 is "1".
DATA Polling (I/O7)
The F29C51001T/F29C51001B features DATA polling to indicate the end of a program cycle. When the device is in the program cycle, any attempt to read the device will received the complement of the loaded data on I/O7. Once the program cycle is completed, I/O7 will show true data, and the device is then ready for the next cycle.
Toggle Bit (I/O6)
The F29C51001T/F29C51001B also features another method for determining the end of a program cycle. When the device is in the program cycle, any attempt to read the device will result in l/O6 toggling between 1 and 0. Once the program is completed, the toggling will stop. The device is then ready for the next operation. Examining the toggle bit may begin at any time during a program cycle.
Program Cycle Status Detection
There are two methods for determining the state of the F29C51001T/F29C51001B during a program (erase/program) cycle: DATA Polling (I/O7) and Toggle Bit (I/O6).
F29C51001T/F29C51001B V1.0 May 1999
10
SyncMOS
Boot Block Protection
The F29C51001T/F29C51001B features hardware Boot Block Protection. The boot block sector protection is enabled when high voltage (12.5V) is applied to OE and A9 pins with CE pin LOW and WE pin lOW. The sector protection is desabled when high voltage is applied to OE, CE and A9 pins with WE pin LOW. Other pins can be HIGH or LOW. This is shown in table 1.
F29C51001T/F29C51001B
Device ID
In Autoselect mode, performing a read at address XXXXH will determine whether the device is a Top Boot Block device or a Bottom Boot Block device. If the data is 01H, the device is a Top Boot Block. If the data is A1H, the device is a Bottom Boot Block device (see Table 3). In addition, the device ID can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the A9 pin. When A0 is HIGH, the device ID is presented at the outputs.
Autoselect
The F29C51001T/F29C51001B features an Autoselect mode to identify the Boot Block (protected/unprotected), the Device (Top/Bottom), and the manufacturer ID. To get to the Autoselect mode, a high voltage (VH) must be applied to the A9 pin. Once the A9 signal is returned to LOW or HIGH, the device will return to the previous mode.
Manufacturer ID
In Autoselect mode, performing a read at address. XXXX0H will determine the manufacturer ID. 40H is the manufacturer code for SyncMOS Flash. In addition the manufacturer ID can also be read via the command register when the device is erased or programmed in a system without applying high voltage to the A9 pin. when A0 is LOW, the manufacturer ID is presented at the outputs.
Boot Block Protection Status
In Autoselect mode, performing a read at address 3CXX2H or address 0CXX2H will indicate if the Top Boot Block sector or the Bottom Boot Block sector is locked out. If the data is 01H, the Top/Bottom Boot Block is protected. If the data is 00H, the Top/Bottom Boot Block is unprotected. (see Table 3.)
Hardware Data Protection
VCC Sense Protection: the program operation is inhibited when VCC is less than 2.5V. Noise Protection: a CE or WE pulse of less than 5ns will not initiate a program cycle. Program Inhibit Protection: holding any one of OE LOW, CE HIGH or WE HIGH inhibits a program cycle.
Table 3. Autoselect Decoding
Address Decoding Mode
Boot Block Protection
Boot Block
Top Bottom
A0
VIL VIL VIH
A1
VIH VIH VIL
A2-A13
X X X
A14-A16
VIH VIL X
Data I/O0-I/O7
01H: protected 00H: unprotected 01H A1H
Device ID
Top Bottom
Manufacture ID NOTE: 1. X = Don't Care, VIH = HIGH, VIL = LOW.
VIL
VIL
X
X
40H
F29C51001T/F29C51001B V1.0 May 1999
11
SyncMOS
Byte Program Algorithm
Write Program Command Sequence
F29C51001T/F29C51001B
Chip/Sector Erase Algorithm
Write Erase Command Sequence
Add/Data 5555H/AAH
Add/Data 5555H/AAH
2AAAH/55H Four Bus Cycle Sequence 5555H/A0H
2AAAH/55H
5555H/80H Six Bus Cycle Sequence
PA/PD
5555H/AAH
DATA Polling (I/O7) or Toggle Bit (I/O6)
2AAAH/55H
No Verify Byte?
5555H/10H (Chip Erase) PA/30H (Sector Erase
Yes Programming Completed
DATA Polling or Toggle Bit Successfully Completed
Erase Complete
51001-14
F29C51001T/F29C51001B V1.0 May 1999
12
SyncMOS
DATA Polling Algorithm
Read I/O7 Address = PBA(1)
F29C51001T/F29C51001B
Toggle Bit Algorithm
Read I/O6
No
I/O7 = Data
Read I/O6
Yes Yes Program Done No I/O6 Toggle
Program Done
51002-17
NOTE: 1. PBA: The byte address to be programmed.
F29C51001T/F29C51001B V1.0 May 1999
13
SyncMOS
Package Diagrams
32-pin Plastic DIP
1.660 MAX.
F29C51001T/F29C51001B
15 MAX
INDEX-1 EJECTOR MARK 0.545/0.555 INDEX-2 .600 TYP
+.004 .010 - .0004
.050 MAX
0.210 MAX 0.120 MIN .100 TYP +.012 .047 - 0 +.006 .018 - .002 0.010 MIN .032 +.012 -0
32-pin PLCC
20 19 18 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 17 16 15 14 13 12 11 10 9 8 7 6 5 .550 .003 .590 .005
.045X45 .450 .003 .490 .005 .050 TYP .110 .136 .003 .046 .003 .025 30
.017
3 - 6
.420 .003
3 - 6
3 - 6
F29C51001T/F29C51001B V1.0 May 1999
14
SyncMOS
32-pin TSOP-I
Units in inches
0.787 0.008
F29C51001T/F29C51001B
Detail "A"
0.010 0.315 TYP. (0.319 MAX.)
0.024 0.004 0.724 TYP. (0.728 MAX.) SEATING PLANE See Detail "A" 0.005 MIN. 0.007 MAX. 0.032 TYP. 0.020 MAX. 0.020 SBC 0.003 MAX 0.009 0.002 0.035 0.002 0.047 MAX.
F29C51001T/F29C51001B V1.0 May 1999
15
SyncMOS Technology Inc.
Sales Office :
No. 1, Creation Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. Tel : 886-3-5792926 Fax : 886-3-5792953
Note 1 : publication date : May 1999. Rev. A Note 2 : all data and specification are subject to change without notice.
F29C51001T/F29C51001B V1.0 May 1999
16

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